The present invention relates to semiconductor devices and more particularly to a bond pad and the physical layout of a bond pad on a semiconductor die.
Bond pads are formed on a semiconductor die to provide means for transferring electrical signals and power to and from circuitry of the semiconductor die via probes, bond wires, conductive bumps, etc. Bond pads are typically arranged in rows along the perimeter of the semiconductor device, or in an array format. To accommodate increases in semiconductor device densities and input/output (I/O) requirements, semiconductor device manufacturers are looking to reduce the spacing between bond pads, known as pitch. However, bond pad pitch reduction poses a number of assembly problems. For example, because spacing between bond wires is reduced when bond pad pitch is reduced, there is an increased risk of wire shorting arising from wire looping and wire trajectory variations and from wire sweep during mold encapsulation; that is, the flow of mold compound pushing wires into contact with each other.
FIG. 1 is an enlarged top plan view of a corner of a conventional semiconductor die 10 having bond pads 12 along its perimeter 14 and FIG. 2 is an enlarged top plan view of one of the bond pads 12. Each of the bond pads 12 may include a bond wire or input/output (IO) pad area 16 for receiving a bond wire, a Power Ground Embedded (PGE) area 18 for an embedded power or embedded ground pad, an IO probe area 20 and a PGE probe area 22. The probe areas 20 and 22 allow for testing of the IO pad area 16 and the PGE area 18, respectively, using test equipment at probe level before the semiconductor die has been packaged. Referring to FIG. 1, the bond pads 12 are laid out in rows along the perimeter 14, and the corner of the die 10 may be either empty or have a corner pad 24. Further, it can be seen that the IO probe areas 20 for the respective rows of bond pads 12 are aligned. That is, the bond pads 12 along the bottom (horizontal) row have their IO probe areas 20 aligned and the bond pads 12 along the side (vertical) row have their IO probe areas 20 aligned.
In order to allow probing of multiple semiconductor dies so as to reduce the test cost, there are certain design rules that must be followed when laying out the bond pads 12 along the perimeter 14 of the die 10. One such rule, sometimes referred to as a corner keep out rule, is that the IO probe area 20A of the bond pad 12A (along the bottom row and closest to the corner) must be separated from the IO probe area 20B of the bond pad 12B (along the side row and closest to the corner) by a minimum predetermined distance, denoted as d. This pre-determined distance d depends upon the probing technique to be used for testing multiple die simultaneously. Unfortunately, this design rule results in a wasted space area 26. Note that the wasted space area 26 occurs at or near all four corners of the die 10. U.S. Patent Publication No. 2009/0051050 proposes accommodating a bond pad inside a corner wasted space area. However, to place the bond pad in the wasted space area 26, the size and layout of the bond pads are altered in such a way that the bond pads near to the corner do not have their probe areas aligned with the probe areas of the other bond pads in the same row (along the same side of the die). Another problem with this approach is that any such bond pad placed in the wasted space area 26 cannot be readily probed without increasing the test time many fold.
Thus, there is a need for a way to increase the number of bond pads on a high density semiconductor device without violating any probing rules yet still allowing for parallel probing so as not to increase test costs.